It is often desirable to decrease the complexity of an image processor that compresses or decompresses image data. Because image data is often arranged in two-dimensional (2-D) blocks, the processor often executes 2-D mathematical functions to process the image data. Unfortunately, a processor having a relatively complex architecture is typically required to execute these complex image-processing functions. The complex architecture often increases the size of the processor's arithmetic unit and its internal data busses, and thus often increases the cost and overall size of the processor as compared to standard processors.
One technique for effectively reducing the complexity of an image processor's architecture is to break down the complex image-processing functions into a series of simpler functions that a simpler architecture can handle. For example, a paper by Masaki et al., which is incorporated by reference, discloses a technique for breaking down an 8-point vector multiplication into a series of 4-point vector multiplications to simplify a 2-D IDCT. VLSI Implementation of Inversed Discrete Cosine Transformer and Motion Compensator for MPEG2 HDTV Video Decoding, IEEE Transactions On Circuits And Systems For Video Technology, Vol. 5, No. 5, October, 1995.
Unfortunately, although such a technique allows the processor to have a simpler architecture, it often increases the time that the processor needs to process the image data. Thus, the general rule is that the simpler the processor's architecture, the slower the processing time, and the more complex the processor's architecture, the faster the processing time.
To help the reader understand the concepts discussed above and those discussed below in the Description of the Invention, following is a basic overview of conventional image compression/decompression techniques, the 2-D DCT function and the 2-D and 1-D IDCT functions, and a discussion of Masaki's technique for simplifying the 1-D IDCT function.